Although increases in power consumption due to leakage currents in wiring layer insulating films have hitherto been known, in generations of semiconductor devices having line spacings greater than 1 μm, the influence of such leakage currents on the overall device has been small. However, at line spacings of 1 μm or below, owing to the narrower spacing between lines and the increase in the scale of the wiring, such leakage currents have a greater influence on power consumption. In particular, as circuits come to be formed at line spacings of 0.1 μm or below, the leakage current between lines will exert a large influence on the characteristics and life of the device.
Wiring in a semiconductor device may be formed by the damascene process in which, first, trenches in the shape of the wiring are formed in an insulating film by etching, following which copper lines are formed in the trenches by plating. However, in this damascene process, because the insulating film invariably incurs damage during etching, the increase in hydrophilicity due to the damage that arises at the interior of the insulating film leads to such effects as an increase in the leakage current and a deterioration in TDDB characteristics, which are major factors in lowering yield and reliability in semiconductor production. It is assumed that this problem will become increasingly severe with the formation of circuits at line spacings of 0.1 μm or below.
In view of the above, there exists a need either to suppress damage during etching of the insulating layer when forming the wiring trenches or to carry out surface treatment to reduce the leakage current after etching.
Surface treatment to hold down the increase in hydrophilicity due to etching damage may include hydrophobicizing the wiring trenches after etching. For example, by using a method in which the etched surface of a silica-based film is hydrophobicized (see Patent Documents 1 to 4) or the like, moisture adsorption to the surface due to etching damage can be reduced, thus making it possible to minimize a deterioration in characteristics due to moisture, such as a rise in the dielectric constant.    Patent Document 1: Japanese Patent Application Laid-open No. H6-267946 (Claims)    Patent Document 2: Japanese Translation of PCT Application No. 2004-511896 (Claims)    Patent Document 3: Japanese Translation of PCT Application No. 2004-513503 (Claims)    Patent Document 4: Japanese Patent Application Laid-open No. 2004-292304 (Claims)